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| HD74LS138 3-Line-to-8-Line Decoders / Demultiplexers REJ03D0434-0300 Rev.3.00 Jul.13.2005 The HD74LS138 decodes one-of-eight line dependent on the conditions at the three binaly select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. Features * Ordering Information Part Name HD74LS138P HD74LS138FPEL HD74LS138RPEL Package Type DILP-16 pin SOP-16 pin (JEITA) SOP-16 pin (JEDEC) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation P FP Taping Abbreviation (Quantity) EL (2,000 pcs/reel) EL (2,500 pcs/reel) PRSP0016DG-A RP (FP-16DNV) Note: Please consult the sales office for the above package availability. Pin Arrangement A Select Inputs B C G2A Enable Inputs G2B G1 1 A 2 3 4 5 6 7 8 B C G2A G2B G1 Y7 Y6 Y0 Y1 Y2 Y3 Y4 Y5 16 15 14 13 12 11 10 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Outputs Outputs Y7 GND (Top view) Rev.3.00, Jul.13.2005, page 1 of 7 HD74LS138 Function Table Inputs Enable G1 G2* X H L X H L H L H L H L H L H L H L H L C X X L L L L H H H H Select B X X L L H H L L H H A X X L H L H L H L H Y0 H H L H H H H H H H Y1 H H H L H H H H H H Y2 H H H H L H H H H H Outputs Y3 H H H H H L H H H H Y4 H H H H H H L H H H Y5 H H H H H H H L H H Y6 H H H H H H H H L H Y7 H H H H H H H H H L H ; high level, L ; low level, X ; irrelevant * ; G2 = G2A + G2B Block Diagram Y0 Y1 Enable Inputs G1 G2A G2B Y2 Y3 Y4 A Select Inputs B C Y5 Y6 Y7 Data Outputs Absolute Maximum Ratings Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Symbol VCC IOH IOL Topr Min 4.75 -- -- -20 Typ 5.00 -- -- 25 Max 5.25 -400 8 75 Unit V A mA C Rev.3.00, Jul.13.2005, page 2 of 7 HD74LS138 Electrical Characteristics (Ta = -20 to +75 C) Item Input voltage Symbol VIH VIL VOH Output voltage VOL IIH IIL II Short-circuit output IOS current Supply current ICC Input clamp voltage VIK Note: * VCC = 5 V, Ta = 25C min. 2.0 -- 2.7 -- -- -- -- -- -20 -- -- typ.* -- -- -- -- -- -- -- -- -- 6.3 -- max. -- 0.8 -- 0.4 0.5 20 -0.4 0.1 -100 10 -1.5 Unit V V V V A mA mA mA mA V Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V, Outputs enabled and open VCC = 4.75 V, IIN = -18 mA Input current Switching Characteristics (VCC = 5 V, Ta = 25C) Item Symbol tPLH tPHL tPLH tPLH tPLH tPHL tPLH tPLH Inputs Binary select A, B, C Enable G2A, G2B Enable G1 Output Levels of delay 2 Y 3 2 Y 3 min. -- -- -- -- -- -- -- -- typ. 13 27 18 26 12 21 17 25 max. 20 41 27 39 18 32 26 38 Unit ns ns ns ns ns ns ns ns Condition Propagation delay time CL = 15 pF, RL = 2 k Rev.3.00, Jul.13.2005, page 3 of 7 HD74LS138 Testing Method Test Circuit VCC 4.5V RL Y0 CL A Input B Output Y1 Output Y2 G1 G2A G2B Y4 Output Y5 Output Y6 Output Y7 Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Y3 Output Same as Load Circuit 1. Output Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Output Load circuit 1 See Testing Table P.G. Zout = 50 C Notes: 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Waveform tTLH 90% 1.3 V 10% tPLH tTHL 90% 1.3 V 10% tPHL VOH In phase Output tPHL 1.3 V tPLH VOH Out of phase Output 1.3 V 1.3 V VOL 1.3 V VOL 3V 0V Input Note: Input pulse; tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz, duty cycle 50% Rev.3.00, Jul.13.2005, page 4 of 7 HD74LS138 Relation Between Input and Output to Levels of Delay Inputs A B C G1 G2A, G2B Y0 Y0 Y0 Outputs 2 levels of delay Y2 Y4 Y1 Y4 Y1 Y2 Y0 to Y7 Y6 Y5 Y3 Y1 Y2 Y4 3 levels of delay Y3 Y5 Y3 Y6 Y5 Y6 Y0 to Y7 Y7 Y7 Y7 Rev.3.00, Jul.13.2005, page 5 of 7 HD74LS138 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g D 16 9 1 0.89 b3 8 Z E A1 A Reference Symbol Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max e D E L 1 A A1 e bp e1 b c b c p 3 e Z ( Ni/Pd/Au plating ) L JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B Previous Code FP-16DAV MASS[Typ.] 0.24g *1 D F 9 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp HE E Index mark Reference Symbol *2 c Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5 Terminal cross section ( Ni/Pd/Au plating ) 1 Z e *3 D E A2 8 bp x M L1 A1 A bp b1 c 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 1 0.20 0.25 A c HE 0 7.50 7.80 1.27 8 8.00 A1 y L e x y 0.12 0.15 0.80 0.50 1 Detail F Z L L 0.70 1.15 0.90 Rev.3.00, Jul.13.2005, page 6 of 7 HD74LS138 JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A Previous Code FP-16DNV MASS[Typ.] 0.15g *1 D 9 F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp Index mark *2 E HE c Reference Symbol Dimension in Millimeters Min Nom 9.90 3.95 Max 10.30 Terminal cross section ( Ni/Pd/Au plating ) 1 Z e *3 D E A2 8 bp x M L1 A1 A bp b1 c c 1 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 HE 0 5.80 6.10 1.27 8 6.20 A A1 L y e x y 0.25 0.15 0.635 0.40 1 Detail F Z L L 0.60 1.08 1.27 Rev.3.00, Jul.13.2005, page 7 of 7 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. 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